FPGA实现usb驱动
2016-08-23
0 0 0
暂无评分
其他
如何获取积分?
应用背景
This is the very first officially available release of the core- It is still under active development
- Please do not modify the sources !
- Things that are not implemented yet, or are known not to work yet:
- UTMI line/link control interface is not implemented yet. This includes:
- Detection of attach/detach
- Speed negotiation (Full/High Speed)
- USB reset
- USB suspend
- There is no logic in the core to "help" suspending it. I'm not
quite sure yet what to do in this area. (Suggestions welcomed !)
- There is no easy way to configure the core (number of endpoints,
buffer size)
- There has been absolutely no testing done on the core
关键技术
This file describes the current status of the checked in HDL code.Please su
verilog
usb
fpga
驱动
实现
相关源码推荐
USB Mass Storage例程(SD卡模拟U盘)(V1.2)
0
0
暂无评分
AXI主机从机功能模型
0
0
暂无评分
axi从机转fifo代码
0
0
暂无评分
基于ahb的DMA控制器
0
0
暂无评分
ldpc码的verilog实现
0
0
暂无评分
暂无评论