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stm32f10x_fsmc.h ( 文件浏览 )

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  • Arthur_zeng 发布于2017-10-26
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			/**
  ******************************************************************************
  * @file  stm32f10x_fsmc.h
  * @author  MCD Application Team
  * @version  V3.0.0
  * @date  04/06/2009
  * @brief  This file contains all the functions prototypes for the FSMC 
  *         firmware library.
  ******************************************************************************
  * @copy
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
  */ 

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FSMC_H
#define __STM32F10x_FSMC_H

/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"

/** @addtogroup StdPeriph_Driver
  * @{

  */

/** @addtogroup FSMC
  * @{

  */

/** @defgroup FSMC_Exported_Types
  * @{

  */

/** 
  * @brief  Timing parameters For NOR/SRAM Banks  
  */

typedef struct
{

  uint32_t FSMC_AddressSetupTime;
  uint32_t FSMC_AddressHoldTime;
  uint32_t FSMC_DataSetupTime;
  uint32_t FSMC_BusTurnAroundDuration;
  uint32_t FSMC_CLKDivision;
  uint32_t FSMC_DataLatency;
  uint32_t FSMC_AccessMode;

}FSMC_NORSRAMTimingInitTypeDef;

/** 
  * @brief  FSMC NOR/SRAM Init structure definition
  */

typedef struct
{

  uint32_t FSMC_Bank;
  uint32_t FSMC_DataAddressMux;
  uint32_t FSMC_MemoryType;
  uint32_t FSMC_MemoryDataWidth;
  uint32_t FSMC_BurstAccessMode;
  uint32_t FSMC_WaitSignalPolarity;
  uint32_t FSMC_WrapMode;
  uint32_t FSMC_WaitSignalActive;
  uint32_t FSMC_WriteOperation;
  uint32_t FSMC_WaitSignal;
  uint32_t FSMC_ExtendedMode;
  uint32_t FSMC_WriteBurst;  
  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;/* Timing Parameters for write and read access if the  ExtendedMode is not used*/
  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;/* Timing Parameters for write access if the  ExtendedMode is used*/

}FSMC_NORSRAMInitTypeDef;

/** 
  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
  */

typedef struct
{

  uint32_t FSMC_SetupTime;
  uint32_t FSMC_WaitSetupTime;
  uint32_t FSMC_HoldSetupTime;
  uint32_t FSMC_HiZSetupTime;

}FSMC_NAND_PCCARDTimingInitTypeDef;

/** 
  * @brief  FSMC NAND Init structure definition
  */

typedef struct
{

  uint32_t FSMC_Bank;
  uint32_t FSMC_Waitfeature;
  uint32_t FSMC_MemoryDataWidth;
  uint32_t FSMC_ECC;
  uint32_t FSMC_ECCPageSize;
  uint32_t FSMC_TCLRSetupTime;
  uint32_t FSMC_TARSetupTime;  
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */ 
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;/* FSMC Attribute Space Timing */

}FSMC_NANDInitTypeDef;

/** 
  * @brief  FSMC PCCARD Init structure definition
  */

typedef struct
{

  uint32_t FSMC_Waitfeature;
  uint32_t FSMC_TCLRSetupTime;
  uint32_t FSMC_TARSetupTime;  
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /* FSMC Attribute Space Timing */
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct;  /* FSMC IO Space Timing */

}FSMC_PCCARDInitTypeDef;

/**
  * @
}
  */

/** @defgroup FSMC_Exported_Constants
  * @{

  */

/** @defgroup FSMC_Banks_definitions 
  * @{

  */

#define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
#define FSMC_Bank1_NORSRAM2                             ((uint32_t)0x00000002)
#define FSMC_Bank1_NORSRAM3                             ((uint32_t)0x00000004)
#define FSMC_Bank1_NORSRAM4                             ((uint32_t)0x00000006)
#define FSMC_Bank2_NAND                                 ((uint32_t)0x00000010)
#define FSMC_Bank3_NAND                                 ((uint32_t)0x00000100)
#define FSMC_Bank4_PCCARD                               ((uint32_t)0x00001000)

#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM4))

#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
                                 ((BANK) == FSMC_Bank3_NAND))

#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
                                    ((BANK) == FSMC_Bank3_NAND) || \
                                    ((BANK) == FSMC_Bank4_PCCARD))

#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
                               ((BANK) == FSMC_Bank3_NAND) || \
                               ((BANK) == FSMC_Bank4_PCCARD))
/**
  * @
}
  */

/** @defgroup NOR_SRAM_Banks 
  * @{

  */

/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
  * @{

  */

#define FSMC_DataAddressMux_Disable                       ((uint32_t)0x00000000)
#define FSMC_DataAddressMux_Enable                        ((uint32_t)0x00000002)
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
                          ((MUX) == FSMC_DataAddressMux_Enable))

/**
  * @
}
  */

/** @defgroup FSMC_Memory_Type 
  * @{

  */

#define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
#define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
#define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
                                ((MEMORY) == FSMC_MemoryType_NOR))

/**
  * @
}
  */

/** @defgroup FSMC_Data_Width 
  * @{

  */

#define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))

/**
  * @
}
  */

/** @defgroup FSMC_Burst_Access_Mode 
  * @{

  */

#define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000) 
#define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
                                  ((STATE) == FSMC_BurstAccessMode_Enable))
/**
  * @
}
  */

/** @defgroup FSMC_Wait_Signal_Polarity 
  * @{

  */

#define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
#define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
                                         ((POLARITY) == FSMC_WaitSignalPolarity_High)) 

/**
  * @
}
  */

/** @defgroup FSMC_Wrap_Mode 
  * @{

  */

#define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
#define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400) 
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
                                 ((MODE) == FSMC_WrapMode_Enable))

/**
  * @
}
  */

/** @defgroup FSMC_Wait_Timing 
  * @{

  */

#define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
#define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800) 
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))

/**
  * @
}
  */

/** @defgroup FSMC_Write_Operation 
  * @{

  */

#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
                                            ((OPERATION) == FSMC_WriteOperation_Enable))
                              
/**
  * @
}
  */

/** @defgroup FSMC_Wait_Signal 
  * @{

  */

#define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
#define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000) 
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
/**
  * @
}
  */

/** @defgroup FSMC_Extended_Mode 
  * @{

  */

#define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
#define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)

#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
                                     ((MODE) == FSMC_ExtendedMode_Enable)) 

/**
  * @
}
  */

/** @defgroup FSMC_Write_Burst 
  * @{

  */

#define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
#define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000) 
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
                                    ((BURST) == FSMC_WriteBurst_Enable))
/**
  * @
}
  */

/** @defgroup FSMC_Address_Setup_Time 
  * @{

  */

#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)

/**
  * @
}
  */

/** @defgroup FSMC_Address_Hold_Time 
  * @{

  */

#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)

/**
  * @
}
  */

/** @defgroup FSMC_Data_Setup_Time 
  * @{

  */

#define IS_FSMC_DATASETUP_TIME(TIME) (((TI
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stm32f10x_rtc.h3.57 kB06-04-09|10:30
stm32f10x_sdio.h18.16 kB06-04-09|10:30
stm32f10x_spi.h14.55 kB06-04-09|10:30
stm32f10x_tim.h47.63 kB06-04-09|10:30
stm32f10x_type.h3.44 kB02-09-09|17:36
stm32f10x_usart.h14.14 kB06-04-09|10:30
stm32f10x_wwdg.h2.72 kB06-04-09|10:30
misc.c6.71 kB06-04-09|10:30
stm32f10x_adc.c45.54 kB06-04-09|10:30
stm32f10x_bkp.c8.05 kB06-04-09|10:30
stm32f10x_can.c30.23 kB06-04-09|10:30
stm32f10x_crc.c3.26 kB06-04-09|10:30
stm32f10x_dac.c13.40 kB06-04-09|10:30
stm32f10x_dbgmcu.c4.21 kB06-04-09|10:30
stm32f10x_dma.c26.72 kB06-04-09|10:30
stm32f10x_exti.c6.64 kB06-04-09|10:30
stm32f10x_flash.c25.73 kB06-04-09|10:30
stm32f10x_fsmc.c34.11 kB06-04-09|10:30
stm32f10x_gpio.c17.47 kB06-04-09|10:30
stm32f10x_i2c.c36.45 kB06-04-09|10:30
stm32f10x_iwdg.c4.70 kB06-04-09|10:30
stm32f10x_pwr.c8.72 kB06-04-09|10:30
stm32f10x_rcc.c32.99 kB06-04-09|10:30
stm32f10x_rtc.c8.38 kB06-04-09|10:30
stm32f10x_sdio.c27.82 kB06-04-09|10:30
stm32f10x_spi.c27.09 kB06-04-09|10:30
stm32f10x_tim.c99.50 kB06-04-09|10:30
stm32f10x_usart.c34.11 kB06-04-09|10:30
stm32f10x_wwdg.c5.49 kB06-04-09|10:30
all-wcprops1.91 kB29-06-11|14:21
entries3.19 kB29-06-11|14:21
can.c.svn-base13.36 kB29-06-11|10:13
can.h.svn-base1.08 kB27-06-11|10:12
GLOBAL.c.svn-base198.00 B29-06-11|10:13
global.h.svn-base1.30 kB29-06-11|10:13
GPIO.c.svn-base999.00 B24-06-11|11:17
GPIO.H.svn-base496.00 B24-06-11|11:17
InitialStm32.c.svn-base1.69 kB24-06-11|11:17
InitialStm32.h.svn-base91.00 B24-06-11|11:17
KMS_Table.h.svn-base5.09 kB24-06-11|11:17
main.c.svn-base2.55 kB29-06-11|10:13
math.h.svn-base39.99 kB24-06-11|11:17
obd.c.svn-base39.57 kB29-06-11|14:21
obd.h.svn-base9.29 kB29-06-11|14:21
stm32f10x_conf.h.svn-base3.13 kB24-06-11|11:17
stm32f10x_it.c.svn-base24.02 kB24-06-11|11:17
stm32f10x_it.h.svn-base1.85 kB24-06-11|11:17
time.c.svn-base3.50 kB24-06-11|11:17
time.h.svn-base245.00 B24-06-11|11:17
USART.C.svn-base6.78 kB24-06-11|11:17
USART.H.svn-base625.00 B24-06-11|11:17
can.c13.36 kB27-06-11|15:04
can.h1.08 kB25-06-11|18:01
GLOBAL.c198.00 B27-06-11|11:46
global.h1.30 kB29-06-11|15:32
GPIO.c999.00 B24-06-11|11:17
GPIO.H496.00 B24-06-11|11:17
InitialStm32.c1.69 kB24-06-11|11:17
InitialStm32.h91.00 B24-06-11|11:17
KMS_Table.h5.09 kB24-06-11|11:17
main.c2.43 kB29-06-11|17:31
math.h39.99 kB24-06-11|11:17
obd.c41.63 kB29-06-11|17:13
obd.h9.17 kB29-06-11|14:32
stm32f10x_conf.h3.13 kB24-06-11|11:17
stm32f10x_it.c24.02 kB24-06-11|11:17
stm32f10x_it.h1.85 kB24-06-11|11:17
time.c3.50 kB24-06-11|11:17
time.h245.00 B24-06-11|11:17
USART.C6.78 kB24-06-11|11:17
USART.H625.00 B24-06-11|11:17
j1939??.doc24.50 kB20-06-11|17:36
~$1939??.doc162.00 B18-06-11|09:19
????.TXT358.00 B20-06-11|11:38
?????.doc25.00 kB20-06-11|16:15
prop-base0.00 B24-06-11|11:17
props0.00 B24-06-11|11:17
text-base0.00 B29-06-11|14:21
inc0.00 B17-06-11|09:35
src0.00 B17-06-11|09:35
prop-base0.00 B24-06-11|11:17
props0.00 B24-06-11|11:17
text-base0.00 B29-06-11|14:21
tmp0.00 B29-06-11|14:21
CMSIS0.00 B17-06-11|09:35
StartUp0.00 B17-06-11|09:35
StdPerphi_Driver0.00 B17-06-11|09:35
.svn0.00 B29-06-11|14:21
list0.00 B17-06-11|09:57
obj0.00 B29-06-11|17:13
lib0.00 B17-06-11|09:35
user0.00 B24-06-11|11:22
insource0.00 B10-10-17|13:37
keil0.00 B29-06-11|17:48
source0.00 B24-06-11|11:20
spec0.00 B10-10-17|14:19
stm32-obdII0.00 B10-10-17|13:36
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