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stm32f10x_sdio.c ( 文件浏览 )

文件源自:OBD-II代码
  • Arthur_zeng 发布于2017-10-26
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			/**
  ******************************************************************************
  * @file  stm32f10x_sdio.c
  * @author  MCD Application Team
  * @version  V3.0.0
  * @date  04/06/2009
  * @brief  This file provides all the SDIO firmware functions.
  ******************************************************************************
  * @copy
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
  */ 

/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_sdio.h"
#include "stm32f10x_rcc.h"

/** @addtogroup StdPeriph_Driver
  * @{

  */

/** @defgroup SDIO 
  * @brief SDIO driver modules
  * @{

  */ 

/** @defgroup SDIO_Private_TypesDefinitions
  * @{

  */ 

/* ------------ SDIO registers bit address in the alias region ----------- */
#define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)

/* --- CLKCR Register ---*/

/* Alias word address of CLKEN bit */
#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
#define CLKEN_BitNumber           0x08
#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))

/* --- CMD Register ---*/

/* Alias word address of SDIOSUSPEND bit */
#define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
#define SDIOSUSPEND_BitNumber     0x0B
#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))

/* Alias word address of ENCMDCOMPL bit */
#define ENCMDCOMPL_BitNumber      0x0C
#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))

/* Alias word address of NIEN bit */
#define NIEN_BitNumber            0x0D
#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))

/* Alias word address of ATACMD bit */
#define ATACMD_BitNumber          0x0E
#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))

/* --- DCTRL Register ---*/

/* Alias word address of DMAEN bit */
#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
#define DMAEN_BitNumber           0x03
#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))

/* Alias word address of RWSTART bit */
#define RWSTART_BitNumber         0x08
#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))

/* Alias word address of RWSTOP bit */
#define RWSTOP_BitNumber          0x09
#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))

/* Alias word address of RWMOD bit */
#define RWMOD_BitNumber           0x0A
#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))

/* Alias word address of SDIOEN bit */
#define SDIOEN_BitNumber          0x0B
#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))

/* ---------------------- SDIO registers bit mask ------------------------ */

/* --- CLKCR Register ---*/

/* CLKCR register clear mask */
#define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100) 

/* --- PWRCTRL Register ---*/

/* SDIO PWRCTRL Mask */
#define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)

/* --- DCTRL Register ---*/

/* SDIO DCTRL Clear Mask */
#define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)

/* --- CMD Register ---*/

/* CMD Register clear mask */
#define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)

/* SDIO RESP Registers Address */
#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))

/**
  * @
}
  */

/** @defgroup SDIO_Private_Defines
  * @{

  */

/**
  * @
}
  */

/** @defgroup SDIO_Private_Macros
  * @{

  */

/**
  * @
}
  */

/** @defgroup SDIO_Private_Variables
  * @{

  */

/**
  * @
}
  */

/** @defgroup SDIO_Private_FunctionPrototypes
  * @{

  */

/**
  * @
}
  */

/** @defgroup SDIO_Private_Functions
  * @{

  */

/**
  * @brief  Deinitializes the SDIO peripheral registers to their default
  *   reset values.
  * @param  None
  * @retval : None
  */
void SDIO_DeInit(void)
{

  SDIO->POWER = 0x00000000;
  SDIO->CLKCR = 0x00000000;
  SDIO->ARG = 0x00000000;
  SDIO->CMD = 0x00000000;
  SDIO->DTIMER = 0x00000000;
  SDIO->DLEN = 0x00000000;
  SDIO->DCTRL = 0x00000000;
  SDIO->ICR = 0x00C007FF;
  SDIO->MASK = 0x00000000;

}

/**
  * @brief  Initializes the SDIO peripheral according to the specified 
  *   parameters in the SDIO_InitStruct.
  * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure 
  *   that contains the configuration information for the SDIO 
  *   peripheral.
  * @retval : None
  */
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
{

  uint32_t tmpreg = 0;
    
  /* Check the parameters */
  assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
  assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
  assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
  assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); 
   
/*---------------------------- SDIO CLKCR Configuration ------------------------*/  
  /* Get the SDIO CLKCR value */
  tmpreg = SDIO->CLKCR;
  
  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
  tmpreg &= CLKCR_CLEAR_MASK;
  
  /* Set CLKDIV bits according to SDIO_ClockDiv value */
  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
  /* Set BYPASS bit according to SDIO_ClockBypass value */
  /* Set WIDBUS bits according to SDIO_BusWide value */
  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
  tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
             SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
             SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); 
  
  /* Write to SDIO CLKCR */
  SDIO->CLKCR = tmpreg;

}

/**
  * @brief  Fills each SDIO_InitStruct member with its default value.
  * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which 
  *   will be initialized.
  * @retval : None
  */
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
{

  /* SDIO_InitStruct members default value */
  SDIO_InitStruct->SDIO_ClockDiv = 0x00;
  SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
  SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
  SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
  SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
  SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;

}

/**
  * @brief  Enables or disables the SDIO Clock.
  * @param NewState: new state of the SDIO Clock.
  *   This parameter can be: ENABLE or DISABLE.
  * @retval : None
  */
void SDIO_ClockCmd(FunctionalState NewState)
{

  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;

}

/**
  * @brief  Sets the power status of the controller.
  * @param SDIO_PowerState: new state of the Power state. 
  *   This parameter can be one of the following values:
  * @arg SDIO_PowerState_OFF
  * @arg SDIO_PowerState_ON
  * @retval : None
  */
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
{

  /* Check the parameters */
  assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
  
  SDIO->POWER &= PWR_PWRCTRL_MASK;
  SDIO->POWER |= SDIO_PowerState;

}

/**
  * @brief  Gets the power status of the controller.
  * @param  None
  * @retval : Power status of the controller. The returned value can
  *   be one of the following:
  * - 0x00: Power OFF
  * - 0x02: Power UP
  * - 0x03: Power ON 
  */
uint32_t SDIO_GetPowerState(void)
{

  return (SDIO->POWER & (~PWR_PWRCTRL_MASK));

}

/**
  * @brief  Enables or disables the SDIO interrupts.
  * @param SDIO_IT: specifies the SDIO interrupt sources to be 
  *   enabled or disabled.
  *   This parameter can be one or a combination of the following values:
  * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  * @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  * @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  * @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  * @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
  * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
  *                        bus mode interrupt
  * @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
  * @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
  * @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
  * @arg SDIO_IT_RXACT:    Data receive in progress interrupt
  * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  * @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
  * @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
  * @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
  * @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
  * @arg SDIO_IT_TXDAVL:   Data available 
...
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stm32f10x_wwdg.h2.72 kB06-04-09|10:30
misc.c6.71 kB06-04-09|10:30
stm32f10x_adc.c45.54 kB06-04-09|10:30
stm32f10x_bkp.c8.05 kB06-04-09|10:30
stm32f10x_can.c30.23 kB06-04-09|10:30
stm32f10x_crc.c3.26 kB06-04-09|10:30
stm32f10x_dac.c13.40 kB06-04-09|10:30
stm32f10x_dbgmcu.c4.21 kB06-04-09|10:30
stm32f10x_dma.c26.72 kB06-04-09|10:30
stm32f10x_exti.c6.64 kB06-04-09|10:30
stm32f10x_flash.c25.73 kB06-04-09|10:30
stm32f10x_fsmc.c34.11 kB06-04-09|10:30
stm32f10x_gpio.c17.47 kB06-04-09|10:30
stm32f10x_i2c.c36.45 kB06-04-09|10:30
stm32f10x_iwdg.c4.70 kB06-04-09|10:30
stm32f10x_pwr.c8.72 kB06-04-09|10:30
stm32f10x_rcc.c32.99 kB06-04-09|10:30
stm32f10x_rtc.c8.38 kB06-04-09|10:30
stm32f10x_sdio.c27.82 kB06-04-09|10:30
stm32f10x_spi.c27.09 kB06-04-09|10:30
stm32f10x_tim.c99.50 kB06-04-09|10:30
stm32f10x_usart.c34.11 kB06-04-09|10:30
stm32f10x_wwdg.c5.49 kB06-04-09|10:30
all-wcprops1.91 kB29-06-11|14:21
entries3.19 kB29-06-11|14:21
can.c.svn-base13.36 kB29-06-11|10:13
can.h.svn-base1.08 kB27-06-11|10:12
GLOBAL.c.svn-base198.00 B29-06-11|10:13
global.h.svn-base1.30 kB29-06-11|10:13
GPIO.c.svn-base999.00 B24-06-11|11:17
GPIO.H.svn-base496.00 B24-06-11|11:17
InitialStm32.c.svn-base1.69 kB24-06-11|11:17
InitialStm32.h.svn-base91.00 B24-06-11|11:17
KMS_Table.h.svn-base5.09 kB24-06-11|11:17
main.c.svn-base2.55 kB29-06-11|10:13
math.h.svn-base39.99 kB24-06-11|11:17
obd.c.svn-base39.57 kB29-06-11|14:21
obd.h.svn-base9.29 kB29-06-11|14:21
stm32f10x_conf.h.svn-base3.13 kB24-06-11|11:17
stm32f10x_it.c.svn-base24.02 kB24-06-11|11:17
stm32f10x_it.h.svn-base1.85 kB24-06-11|11:17
time.c.svn-base3.50 kB24-06-11|11:17
time.h.svn-base245.00 B24-06-11|11:17
USART.C.svn-base6.78 kB24-06-11|11:17
USART.H.svn-base625.00 B24-06-11|11:17
can.c13.36 kB27-06-11|15:04
can.h1.08 kB25-06-11|18:01
GLOBAL.c198.00 B27-06-11|11:46
global.h1.30 kB29-06-11|15:32
GPIO.c999.00 B24-06-11|11:17
GPIO.H496.00 B24-06-11|11:17
InitialStm32.c1.69 kB24-06-11|11:17
InitialStm32.h91.00 B24-06-11|11:17
KMS_Table.h5.09 kB24-06-11|11:17
main.c2.43 kB29-06-11|17:31
math.h39.99 kB24-06-11|11:17
obd.c41.63 kB29-06-11|17:13
obd.h9.17 kB29-06-11|14:32
stm32f10x_conf.h3.13 kB24-06-11|11:17
stm32f10x_it.c24.02 kB24-06-11|11:17
stm32f10x_it.h1.85 kB24-06-11|11:17
time.c3.50 kB24-06-11|11:17
time.h245.00 B24-06-11|11:17
USART.C6.78 kB24-06-11|11:17
USART.H625.00 B24-06-11|11:17
j1939??.doc24.50 kB20-06-11|17:36
~$1939??.doc162.00 B18-06-11|09:19
????.TXT358.00 B20-06-11|11:38
?????.doc25.00 kB20-06-11|16:15
prop-base0.00 B24-06-11|11:17
props0.00 B24-06-11|11:17
text-base0.00 B29-06-11|14:21
inc0.00 B17-06-11|09:35
src0.00 B17-06-11|09:35
prop-base0.00 B24-06-11|11:17
props0.00 B24-06-11|11:17
text-base0.00 B29-06-11|14:21
tmp0.00 B29-06-11|14:21
CMSIS0.00 B17-06-11|09:35
StartUp0.00 B17-06-11|09:35
StdPerphi_Driver0.00 B17-06-11|09:35
.svn0.00 B29-06-11|14:21
list0.00 B17-06-11|09:57
obj0.00 B29-06-11|17:13
lib0.00 B17-06-11|09:35
user0.00 B24-06-11|11:22
insource0.00 B10-10-17|13:37
keil0.00 B29-06-11|17:48
source0.00 B24-06-11|11:20
spec0.00 B10-10-17|14:19
stm32-obdII0.00 B10-10-17|13:36
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