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stm32f10x_cec.c ( 文件浏览 )

  • aaa923124003 发布于2018-04-23
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			/**
  ******************************************************************************
  * @file    stm32f10x_cec.c
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    11-March-2011
  * @brief   This file provides all the CEC firmware functions.
  ******************************************************************************
  * @attention
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_cec.h"
#include "stm32f10x_rcc.h"

/** @addtogroup STM32F10x_StdPeriph_Driver
  * @{

  */

/** @defgroup CEC 
  * @brief CEC driver modules
  * @{

  */

/** @defgroup CEC_Private_TypesDefinitions
  * @{

  */

/**
  * @
}
  */


/** @defgroup CEC_Private_Defines
  * @{

  */ 

/* ------------ CEC registers bit address in the alias region ----------- */
#define CEC_OFFSET                (CEC_BASE - PERIPH_BASE)

/* --- CFGR Register ---*/

/* Alias word address of PE bit */
#define CFGR_OFFSET                 (CEC_OFFSET + 0x00)
#define PE_BitNumber                0x00
#define CFGR_PE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))

/* Alias word address of IE bit */
#define IE_BitNumber                0x01
#define CFGR_IE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))

/* --- CSR Register ---*/

/* Alias word address of TSOM bit */
#define CSR_OFFSET                  (CEC_OFFSET + 0x10)
#define TSOM_BitNumber              0x00
#define CSR_TSOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))

/* Alias word address of TEOM bit */
#define TEOM_BitNumber              0x01
#define CSR_TEOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
  
#define CFGR_CLEAR_Mask            (uint8_t)(0xF3)        /* CFGR register Mask */
#define FLAG_Mask                  ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
 
/**
  * @
}
  */ 


/** @defgroup CEC_Private_Macros
  * @{

  */ 

/**
  * @
}
  */ 


/** @defgroup CEC_Private_Variables
  * @{

  */ 

/**
  * @
}
  */ 


/** @defgroup CEC_Private_FunctionPrototypes
  * @{

  */
 
/**
  * @
}
  */ 


/** @defgroup CEC_Private_Functions
  * @{

  */ 

/**
  * @brief  Deinitializes the CEC peripheral registers to their default reset 
  *         values.
  * @param  None
  * @retval None
  */
void CEC_DeInit(void)
{

  /* Enable CEC reset state */
  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);  
  /* Release CEC from reset state */
  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 

}


/**
  * @brief  Initializes the CEC peripheral according to the specified 
  *         parameters in the CEC_InitStruct.
  * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
  *         contains the configuration information for the specified
  *         CEC peripheral.
  * @retval None
  */
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
{

  uint16_t tmpreg = 0;
 
  /* Check the parameters */
  assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 
  assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
     
  /*---------------------------- CEC CFGR Configuration -----------------*/
  /* Get the CEC CFGR value */
  tmpreg = CEC->CFGR;
  
  /* Clear BTEM and BPEM bits */
  tmpreg &= CFGR_CLEAR_Mask;
  
  /* Configure CEC: Bit Timing Error and Bit Period Error */
  tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);

  /* Write to CEC CFGR  register*/
  CEC->CFGR = tmpreg;
  

}

/**
  * @brief  Enables or disables the specified CEC peripheral.
  * @param  NewState: new state of the CEC peripheral. 
  *     This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void CEC_Cmd(FunctionalState NewState)
{

  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;

  if(NewState == DISABLE)
  {

    /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
    while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
    {

    
}  
  
}  

}

/**
  * @brief  Enables or disables the CEC interrupt.
  * @param  NewState: new state of the CEC interrupt.
  *   This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void CEC_ITConfig(FunctionalState NewState)
{

  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;

}

/**
  * @brief  Defines the Own Address of the CEC device.
  * @param  CEC_OwnAddress: The CEC own address
  * @retval None
  */
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
{

  /* Check the parameters */
  assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));

  /* Set the CEC own address */
  CEC->OAR = CEC_OwnAddress;

}

/**
  * @brief  Sets the CEC prescaler value.
  * @param  CEC_Prescaler: CEC prescaler new value
  * @retval None
  */
void CEC_SetPrescaler(uint16_t CEC_Prescaler)
{

  /* Check the parameters */
  assert_param(IS_CEC_PRESCALER(CEC_Prescaler));

  /* Set the  Prescaler value*/
  CEC->PRES = CEC_Prescaler;

}

/**
  * @brief  Transmits single data through the CEC peripheral.
  * @param  Data: the data to transmit.
  * @retval None
  */
void CEC_SendDataByte(uint8_t Data)
{
  
  /* Transmit Data */
  CEC->TXD = Data ;

}


/**
  * @brief  Returns the most recent received data by the CEC peripheral.
  * @param  None
  * @retval The received data.
  */
uint8_t CEC_ReceiveDataByte(void)
{

  /* Receive Data */
  return (uint8_t)(CEC->RXD);

}

/**
  * @brief  Starts a new message.
  * @param  None
  * @retval None
  */
void CEC_StartOfMessage(void)
{
  
  /* Starts of new message */
  *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;

}

/**
  * @brief  Transmits message with or without an EOM bit.
  * @param  NewState: new state of the CEC Tx End Of Message. 
  *     This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void CEC_EndOfMessageCmd(FunctionalState NewState)
{
   
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  /* The data byte will be transmitted with or without an EOM bit*/
  *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;

}

/**
  * @brief  Gets the CEC flag status
  * @param  CEC_FLAG: specifies the CEC flag to check. 
  *   This parameter can be one of the following values:
  *     @arg CEC_FLAG_BTE: Bit Timing Error
  *     @arg CEC_FLAG_BPE: Bit Period Error
  *     @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
  *     @arg CEC_FLAG_SBE: Start Bit Error
  *     @arg CEC_FLAG_ACKE: Block Acknowledge Error
  *     @arg CEC_FLAG_LINE: Line Error
  *     @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
  *     @arg CEC_FLAG_TEOM: Tx End Of Message 
  *     @arg CEC_FLAG_TERR: Tx Error
  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
  *     @arg CEC_FLAG_RSOM: Rx
...
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01.97 kB
01.97 kB
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stm32f10x_can.h26.91 kB2011-03-10|10:47
stm32f10x_cec.h6.42 kB2011-03-10|10:47
stm32f10x_crc.h2.11 kB2011-03-10|10:47
stm32f10x_dac.h14.88 kB2011-03-10|10:47
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stm32f10x_dma.h20.27 kB2011-03-10|10:47
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stm32f10x_fsmc.h26.38 kB2011-03-10|10:47
stm32f10x_gpio.h19.70 kB2017-10-13|22:36
stm32f10x_i2c.h29.33 kB2011-03-10|10:47
stm32f10x_iwdg.h3.74 kB2011-03-10|10:47
stm32f10x_pwr.h4.28 kB2011-03-10|10:47
stm32f10x_rcc.h29.74 kB2011-03-10|10:47
stm32f10x_rtc.h3.77 kB2011-03-10|10:47
stm32f10x_sdio.h21.35 kB2011-03-10|10:47
stm32f10x_spi.h17.31 kB2011-03-10|10:47
stm32f10x_tim.h51.20 kB2011-03-10|10:47
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stm32f10x_dma.c28.91 kB2011-03-10|10:47
stm32f10x_exti.c6.80 kB2011-03-10|10:47
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stm32f10x_fsmc.c34.65 kB2011-03-10|10:47
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stm32f10x_pwr.c8.55 kB2011-03-10|10:47
stm32f10x_rcc.c50.07 kB2011-03-10|10:47
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stm32f10x_sdio.c28.25 kB2011-03-10|10:47
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stm32f10x_i2c.d1.62 kB2017-12-17|23:19
stm32f10x_i2c.o382.00 kB2017-12-17|23:19
stm32f10x_it.crf339.63 kB2017-12-17|23:19
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stm32f10x_pwr.o372.05 kB2017-12-17|23:19
stm32f10x_rcc.crf347.10 kB2017-12-17|23:19
stm32f10x_rcc.d1.62 kB2017-12-17|23:19
stm32f10x_rcc.o381.23 kB2017-12-17|23:19
stm32f10x_rtc.crf341.02 kB2017-12-17|23:19
stm32f10x_rtc.d1.62 kB2017-12-17|23:19
stm32f10x_rtc.o372.94 kB2017-12-17|23:19
stm32f10x_sdio.crf344.20 kB2017-12-17|23:19
stm32f10x_sdio.d1.65 kB2017-12-17|23:19
stm32f10x_sdio.o378.45 kB2017-12-17|23:19
stm32f10x_spi.crf344.07 kB2017-12-17|23:19
stm32f10x_spi.d1.62 kB2017-12-17|23:19
stm32f10x_spi.o378.19 kB2017-12-17|23:19
stm32f10x_tim.crf361.76 kB2017-12-17|23:19
stm32f10x_tim.d1.62 kB2017-12-17|23:19
stm32f10x_tim.o404.37 kB2017-12-17|23:19
stm32f10x_usart.crf345.67 kB2017-12-17|23:19
stm32f10x_usart.d1.69 kB2017-12-17|23:19
stm32f10x_usart.o380.94 kB2017-12-17|23:19
stm32f10x_wwdg.crf340.29 kB2017-12-17|23:19
stm32f10x_wwdg.d1.65 kB2017-12-17|23:19
stm32f10x_wwdg.o371.44 kB2017-12-17|23:19
sys.crf342.48 kB2017-12-17|23:19
sys.d1.30 kB2017-12-17|23:19
sys.o375.83 kB2017-12-17|23:19
system_stm32f10x.crf341.32 kB2017-12-17|23:19
system_stm32f10x.d1.62 kB2017-12-17|23:19
system_stm32f10x.o371.02 kB2017-12-17|23:19
template.axf555.93 kB2017-12-17|23:19
template.build_log.htm204.00 B2017-12-18|10:43
template.hex31.47 kB2017-12-17|23:19
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template.lnp1.09 kB2017-12-17|23:19
template.sct479.00 B2017-11-26|10:06
usart.crf346.12 kB2017-12-17|23:19
usart.d1.46 kB2017-12-17|23:19
usart.o376.92 kB2017-12-17|23:19
01.97 kB
remote.c5.26 kB2017-12-07|12:43
remote.h877.00 B2017-12-07|12:51
01.97 kB
01.97 kB
delay.c7.74 kB2017-12-06|20:53
delay.h1.94 kB2017-12-06|20:53
01.97 kB
sys.c5.10 kB2017-12-17|23:19
sys.h2.98 kB2017-12-17|23:19
01.97 kB
usart.c4.97 kB2015-03-23|12:28
usart.h1.25 kB2012-09-13|14:17
01.97 kB
main.c4.46 kB2017-12-17|23:19
Release_Notes.html29.41 kB2011-04-06|18:15
startup_stm32f10x_hd.lst49.81 kB2017-12-17|23:19
stm32f10x.h619.08 kB2011-03-10|10:51
stm32f10x_conf.h3.18 kB2017-10-14|09:49
stm32f10x_it.c4.30 kB2011-04-04|19:03
stm32f10x_it.h2.04 kB2011-04-04|19:03
system_stm32f10x.c35.70 kB2011-04-04|19:03
system_stm32f10x.h2.04 kB2011-03-10|10:51
template.build_log.htm7.28 kB2017-10-14|09:38
template.map89.78 kB2017-12-17|23:19
template.uvgui.ZHENG70.76 kB2017-12-18|10:43
template.uvgui_ZHENG.bak70.58 kB2017-12-14|10:32
template.uvopt19.72 kB2017-12-07|15:36
template.uvproj21.42 kB2017-12-07|15:36
template_Target55.85 kB2017-12-17|23:19
template_uvopt.bak18.77 kB2017-11-26|10:06
template_uvproj.bak20.94 kB2017-11-26|10:06
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