CodeForge QQ客服 CodeForge 400电话 客服电话 4006316121

stm32f10x_rcc.c ( 文件浏览 )

  • aaa923124003 发布于2018-04-23
  • 浏览次数:0
  • 下载次数:0
  • 下载需 1 积分
  • 侵权举报
			/**
  ******************************************************************************
  * @file    stm32f10x_rcc.c
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    11-March-2011
  * @brief   This file provides all the RCC firmware functions.
  ******************************************************************************
  * @attention
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_rcc.h"

/** @addtogroup STM32F10x_StdPeriph_Driver
  * @{

  */

/** @defgroup RCC 
  * @brief RCC driver modules
  * @{

  */ 

/** @defgroup RCC_Private_TypesDefinitions
  * @{

  */

/**
  * @
}
  */

/** @defgroup RCC_Private_Defines
  * @{

  */

/* ------------ RCC registers bit address in the alias region ----------- */
#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)

/* --- CR Register ---*/

/* Alias word address of HSION bit */
#define CR_OFFSET                 (RCC_OFFSET + 0x00)
#define HSION_BitNumber           0x00
#define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))

/* Alias word address of PLLON bit */
#define PLLON_BitNumber           0x18
#define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))

#ifdef STM32F10X_CL
 /* Alias word address of PLL2ON bit */
 #define PLL2ON_BitNumber          0x1A
 #define CR_PLL2ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))

 /* Alias word address of PLL3ON bit */
 #define PLL3ON_BitNumber          0x1C
 #define CR_PLL3ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
#endif /* STM32F10X_CL */ 

/* Alias word address of CSSON bit */
#define CSSON_BitNumber           0x13
#define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))

/* --- CFGR Register ---*/

/* Alias word address of USBPRE bit */
#define CFGR_OFFSET               (RCC_OFFSET + 0x04)

#ifndef STM32F10X_CL
 #define USBPRE_BitNumber          0x16
 #define CFGR_USBPRE_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
#else
 #define OTGFSPRE_BitNumber        0x16
 #define CFGR_OTGFSPRE_BB          (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
#endif /* STM32F10X_CL */ 

/* --- BDCR Register ---*/

/* Alias word address of RTCEN bit */
#define BDCR_OFFSET               (RCC_OFFSET + 0x20)
#define RTCEN_BitNumber           0x0F
#define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))

/* Alias word address of BDRST bit */
#define BDRST_BitNumber           0x10
#define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))

/* --- CSR Register ---*/

/* Alias word address of LSION bit */
#define CSR_OFFSET                (RCC_OFFSET + 0x24)
#define LSION_BitNumber           0x00
#define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))

#ifdef STM32F10X_CL
/* --- CFGR2 Register ---*/

 /* Alias word address of I2S2SRC bit */
 #define CFGR2_OFFSET              (RCC_OFFSET + 0x2C)
 #define I2S2SRC_BitNumber         0x11
 #define CFGR2_I2S2SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))

 /* Alias word address of I2S3SRC bit */
 #define I2S3SRC_BitNumber         0x12
 #define CFGR2_I2S3SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
#endif /* STM32F10X_CL */

/* ---------------------- RCC registers bit mask ------------------------ */

/* CR register bit mask */
#define CR_HSEBYP_Reset           ((uint32_t)0xFFFBFFFF)
#define CR_HSEBYP_Set             ((uint32_t)0x00040000)
#define CR_HSEON_Reset            ((uint32_t)0xFFFEFFFF)
#define CR_HSEON_Set              ((uint32_t)0x00010000)
#define CR_HSITRIM_Mask           ((uint32_t)0xFFFFFF07)

/* CFGR register bit mask */
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
 #define CFGR_PLL_Mask            ((uint32_t)0xFFC2FFFF)
#else
 #define CFGR_PLL_Mask            ((uint32_t)0xFFC0FFFF)
#endif /* STM32F10X_CL */ 

#define CFGR_PLLMull_Mask         ((uint32_t)0x003C0000)
#define CFGR_PLLSRC_Mask          ((uint32_t)0x00010000)
#define CFGR_PLLXTPRE_Mask        ((uint32_t)0x00020000)
#define CFGR_SWS_Mask             ((uint32_t)0x0000000C)
#define CFGR_SW_Mask              ((uint32_t)0xFFFFFFFC)
#define CFGR_HPRE_Reset_Mask      ((uint32_t)0xFFFFFF0F)
#define CFGR_HPRE_Set_Mask        ((uint32_t)0x000000F0)
#define CFGR_PPRE1_Reset_Mask     ((uint32_t)0xFFFFF8FF)
#define CFGR_PPRE1_Set_Mask       ((uint32_t)0x00000700)
#define CFGR_PPRE2_Reset_Mask     ((uint32_t)0xFFFFC7FF)
#define CFGR_PPRE2_Set_Mask       ((uint32_t)0x00003800)
#define CFGR_ADCPRE_Reset_Mask    ((uint32_t)0xFFFF3FFF)
#define CFGR_ADCPRE_Set_Mask      ((uint32_t)0x0000C000)

/* CSR register bit mask */
#define CSR_RMVF_Set              ((uint32_t)0x01000000)

#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
/* CFGR2 register bit mask */
 #define CFGR2_PREDIV1SRC         ((uint32_t)0x00010000)
 #define CFGR2_PREDIV1            ((uint32_t)0x0000000F)
#endif
#ifdef STM32F10X_CL
 #define CFGR2_PREDIV2            ((uint32_t)0x000000F0)
 #define CFGR2_PLL2MUL            ((uint32_t)0x00000F00)
 #define CFGR2_PLL3MUL            ((uint32_t)0x0000F000)
#endif /* STM32F10X_CL */ 

/* RCC Flag Mask */
#define FLAG_Mask                 ((uint8_t)0x1F)

/* CIR register byte 2 (Bits[15:8]) base address */
#define CIR_BYTE2_ADDRESS         ((uint32_t)0x40021009)

/* CIR register byte 3 (Bits[23:16]) base address */
#define CIR_BYTE3_ADDRESS         ((uint32_t)0x4002100A)

/* CFGR register byte 4 (Bits[31:24]) base address */
#define CFGR_BYTE4_ADDRESS        ((uint32_t)0x40021007)

/* BDCR register base address */
#define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)

/**
  * @
}
  */ 

/** @defgroup RCC_Private_Macros
  * @{

  */ 

/**
  * @
}
  */ 

/** @defgroup RCC_Private_Variables
  * @{

  */ 

static __I uint8_t APBAHBPrescTable[16] = {
0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9
};
static __I uint8_t ADCPrescTable[4] = {
2, 4, 6, 8
};

/**
  * @
}
  */

/** @defgroup RCC_Private_FunctionPrototypes
  * @{

  */

/**
  * @
}
  */

/** @defgroup RCC_Private_Functions
  * @{

  */

/**
  * @brief  Resets the RCC clock configuration to the default reset state.
  * @param  None
  * @retval None
  */
void RCC_DeInit(void)
{

  /* Set HSION bit */
  RCC->CR |= (uint32_t)0x00000001;

  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#ifndef STM32F10X_CL
  RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
  RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* STM32F10X_CL */   
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= (uint32_t)0xFEF6FFFF;

  /* Reset HSEBYP bit */
  RCC->CR &= (uint32_t)0xFFFBFFFF;

  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= (uint32_t)0xFF80FFFF;

#ifdef STM32F10X_CL
  /* Reset PLL2ON and PLL3ON bits */
  RCC->CR &= (uint32_t)0xEBFFFFFF;

  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x00FF0000;

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000;

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000;      
#else
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000;
#endif /* STM32F10X_CL */


}

/**
  * @brief  Configures the External High Speed oscillator (HSE).
  * @note   HSE can not be stopped if it is used directly or through the PLL as system clock.
  * @param  RCC_HSE: specifies the new state of the HSE.
  *   This parameter can be one of the following values:
  *     @arg RCC_HSE_OFF: HSE oscillator OFF
  *     @arg RCC_HSE_ON: HSE oscillator ON
  *     @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
  * @retval None
  */
void RCC_HSEConfig(uint32_t RCC_HSE)
{

  /* Check the parameters */
  assert_param(IS_RCC_HSE(RCC_HSE));
  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
  /* Reset HSEON bit */
  RCC->CR &= CR_HSEON_Reset;
  /* Reset HSEBYP bit */
  RCC->CR &= CR_HSEBYP_Reset;
  /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
  switch(RCC_HSE)
  {

    case RCC_HSE_ON:
      /* Set HSEON bit */
      RCC->CR |= CR_HSEON_Set;
      break;
      
    case RCC_HSE_Bypass:
      /* Set HSEBYP and HSEON bits */
      RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
      break;
      
    default:
      break;
  
}

}

/**
  * @brief  Waits for HSE start-up.
  * @param  None
  * @retval An ErrorStatus enumuration value:
  * - SUCCESS: HSE oscillator is stable and ready to use
  * - ERROR: HSE oscillator not yet ready
  */
ErrorStatus RCC_WaitForHSEStartUp(void)
{

  __IO uint32_t StartUpCounter = 0;
  ErrorStatus status = ERROR;
  FlagStatus HSEStatus = RESET;
  
  /* Wait till HSE is ready and if Time out is reached exit */
  do
  {

    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
    StartUpCounter++;  
  
} while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
  

...
...
(文件超长,未完全显示,请下载后阅读剩余部分)
			
...
展开> <收缩

下载源码到电脑,阅读使用更方便

1 积分

快速下载
还剩0行未阅读,继续阅读
云测速

源码文件列表

温馨提示: 点击源码文件名可预览文件内容哦 ^_^
...
名称 大小 修改日期
01.97 kB
01.97 kB
core_cm3.c16.87 kB2010-06-07|10:25
core_cm3.h83.71 kB2011-02-09|14:59
startup_stm32f10x_hd.s15.14 kB2011-03-10|10:52
01.97 kB
01.97 kB
misc.h8.77 kB2011-03-10|10:47
stm32f10x_adc.h21.18 kB2011-03-10|10:47
stm32f10x_bkp.h7.38 kB2011-03-10|10:47
stm32f10x_can.h26.91 kB2011-03-10|10:47
stm32f10x_cec.h6.42 kB2011-03-10|10:47
stm32f10x_crc.h2.11 kB2011-03-10|10:47
stm32f10x_dac.h14.88 kB2011-03-10|10:47
stm32f10x_dbgmcu.h3.73 kB2011-03-10|10:47
stm32f10x_dma.h20.27 kB2011-03-10|10:47
stm32f10x_exti.h6.66 kB2011-03-10|10:47
stm32f10x_flash.h24.85 kB2011-03-10|10:47
stm32f10x_fsmc.h26.38 kB2011-03-10|10:47
stm32f10x_gpio.h19.70 kB2017-10-13|22:36
stm32f10x_i2c.h29.33 kB2011-03-10|10:47
stm32f10x_iwdg.h3.74 kB2011-03-10|10:47
stm32f10x_pwr.h4.28 kB2011-03-10|10:47
stm32f10x_rcc.h29.74 kB2011-03-10|10:47
stm32f10x_rtc.h3.77 kB2011-03-10|10:47
stm32f10x_sdio.h21.35 kB2011-03-10|10:47
stm32f10x_spi.h17.31 kB2011-03-10|10:47
stm32f10x_tim.h51.20 kB2011-03-10|10:47
stm32f10x_usart.h16.16 kB2011-03-10|10:47
stm32f10x_wwdg.h2.90 kB2011-03-10|10:47
01.97 kB
misc.c6.88 kB2011-03-10|10:47
stm32f10x_adc.c46.09 kB2011-03-10|10:47
stm32f10x_bkp.c8.26 kB2011-03-10|10:47
stm32f10x_can.c44.05 kB2011-03-10|10:47
stm32f10x_cec.c11.38 kB2011-03-10|10:47
stm32f10x_crc.c3.27 kB2011-03-10|10:47
stm32f10x_dac.c18.64 kB2011-03-10|10:47
stm32f10x_dbgmcu.c5.03 kB2011-03-10|10:47
stm32f10x_dma.c28.91 kB2011-03-10|10:47
stm32f10x_exti.c6.80 kB2011-03-10|10:47
stm32f10x_flash.c61.08 kB2011-03-10|10:47
stm32f10x_fsmc.c34.65 kB2011-03-10|10:47
stm32f10x_gpio.c22.68 kB2011-03-11|17:43
stm32f10x_i2c.c44.71 kB2011-03-10|10:47
stm32f10x_iwdg.c4.80 kB2011-03-10|10:47
stm32f10x_pwr.c8.55 kB2011-03-10|10:47
stm32f10x_rcc.c50.07 kB2011-03-10|10:47
stm32f10x_rtc.c8.40 kB2011-03-10|10:47
stm32f10x_sdio.c28.25 kB2011-03-10|10:47
stm32f10x_spi.c29.52 kB2011-03-10|10:47
stm32f10x_tim.c106.60 kB2011-03-10|10:47
stm32f10x_usart.c37.41 kB2011-03-10|10:47
stm32f10x_wwdg.c5.60 kB2011-03-10|10:47
01.97 kB
morot.c2.52 kB2017-12-17|23:08
motor.h1.57 kB2017-12-17|23:09
01.97 kB
core_cm3.crf3.57 kB2017-12-17|23:19
core_cm3.d104.00 B2017-12-17|23:19
core_cm3.o10.54 kB2017-12-17|23:19
delay.crf341.66 kB2017-12-17|23:19
delay.d1.41 kB2017-12-17|23:19
delay.o373.57 kB2017-12-17|23:19
main.crf348.30 kB2017-12-17|23:19
main.d1.50 kB2017-12-17|23:19
main.o381.77 kB2017-12-17|23:19
misc.crf340.19 kB2017-12-17|23:19
misc.d1.33 kB2017-12-17|23:19
misc.o370.69 kB2017-12-17|23:19
morot.crf347.94 kB2017-12-17|23:19
morot.d1.43 kB2017-12-17|23:19
morot.o378.45 kB2017-12-17|23:19
remote.crf346.86 kB2017-12-17|23:19
remote.d1.57 kB2017-12-17|23:19
remote.o379.29 kB2017-12-17|23:19
startup_stm32f10x_hd.d63.00 B2017-12-17|23:19
startup_stm32f10x_hd.o6.65 kB2017-12-17|23:19
stm32f10x_adc.crf347.19 kB2017-12-17|23:19
stm32f10x_adc.d1.62 kB2017-12-17|23:19
stm32f10x_adc.o384.34 kB2017-12-17|23:19
stm32f10x_bkp.crf341.11 kB2017-12-17|23:19
stm32f10x_bkp.d1.62 kB2017-12-17|23:19
stm32f10x_bkp.o373.05 kB2017-12-17|23:19
stm32f10x_can.crf348.76 kB2017-12-17|23:19
stm32f10x_can.d1.62 kB2017-12-17|23:19
stm32f10x_can.o381.59 kB2017-12-17|23:19
stm32f10x_cec.crf341.65 kB2017-12-17|23:19
stm32f10x_cec.d1.62 kB2017-12-17|23:19
stm32f10x_cec.o373.47 kB2017-12-17|23:19
stm32f10x_crc.crf339.75 kB2017-12-17|23:19
stm32f10x_crc.d1.62 kB2017-12-17|23:19
stm32f10x_crc.o370.60 kB2017-12-17|23:19
stm32f10x_dac.crf341.78 kB2017-12-17|23:19
stm32f10x_dac.d1.62 kB2017-12-17|23:19
stm32f10x_dac.o373.62 kB2017-12-17|23:19
stm32f10x_dbgmcu.crf339.55 kB2017-12-17|23:19
stm32f10x_dbgmcu.d1.72 kB2017-12-17|23:19
stm32f10x_dbgmcu.o369.86 kB2017-12-17|23:19
stm32f10x_dma.crf343.22 kB2017-12-17|23:19
stm32f10x_dma.d1.62 kB2017-12-17|23:19
stm32f10x_dma.o374.23 kB2017-12-17|23:19
stm32f10x_exti.crf340.73 kB2017-12-17|23:19
stm32f10x_exti.d1.65 kB2017-12-17|23:19
stm32f10x_exti.o371.53 kB2017-12-17|23:19
stm32f10x_flash.crf347.03 kB2017-12-17|23:19
stm32f10x_flash.d1.69 kB2017-12-17|23:19
stm32f10x_flash.o380.89 kB2017-12-17|23:19
stm32f10x_fsmc.crf345.57 kB2017-12-17|23:19
stm32f10x_fsmc.d1.65 kB2017-12-17|23:19
stm32f10x_fsmc.o377.03 kB2017-12-17|23:19
stm32f10x_gpio.crf343.60 kB2017-12-17|23:19
stm32f10x_gpio.d1.65 kB2017-12-17|23:19
stm32f10x_gpio.o376.90 kB2017-12-17|23:19
stm32f10x_i2c.crf345.98 kB2017-12-17|23:19
stm32f10x_i2c.d1.62 kB2017-12-17|23:19
stm32f10x_i2c.o382.00 kB2017-12-17|23:19
stm32f10x_it.crf339.63 kB2017-12-17|23:19
stm32f10x_it.d1.54 kB2017-12-17|23:19
stm32f10x_it.o371.13 kB2017-12-17|23:19
stm32f10x_iwdg.crf339.85 kB2017-12-17|23:19
stm32f10x_iwdg.d1.65 kB2017-12-17|23:19
stm32f10x_iwdg.o370.51 kB2017-12-17|23:19
stm32f10x_pwr.crf341.02 kB2017-12-17|23:19
stm32f10x_pwr.d1.62 kB2017-12-17|23:19
stm32f10x_pwr.o372.05 kB2017-12-17|23:19
stm32f10x_rcc.crf347.10 kB2017-12-17|23:19
stm32f10x_rcc.d1.62 kB2017-12-17|23:19
stm32f10x_rcc.o381.23 kB2017-12-17|23:19
stm32f10x_rtc.crf341.02 kB2017-12-17|23:19
stm32f10x_rtc.d1.62 kB2017-12-17|23:19
stm32f10x_rtc.o372.94 kB2017-12-17|23:19
stm32f10x_sdio.crf344.20 kB2017-12-17|23:19
stm32f10x_sdio.d1.65 kB2017-12-17|23:19
stm32f10x_sdio.o378.45 kB2017-12-17|23:19
stm32f10x_spi.crf344.07 kB2017-12-17|23:19
stm32f10x_spi.d1.62 kB2017-12-17|23:19
stm32f10x_spi.o378.19 kB2017-12-17|23:19
stm32f10x_tim.crf361.76 kB2017-12-17|23:19
stm32f10x_tim.d1.62 kB2017-12-17|23:19
stm32f10x_tim.o404.37 kB2017-12-17|23:19
stm32f10x_usart.crf345.67 kB2017-12-17|23:19
stm32f10x_usart.d1.69 kB2017-12-17|23:19
stm32f10x_usart.o380.94 kB2017-12-17|23:19
stm32f10x_wwdg.crf340.29 kB2017-12-17|23:19
stm32f10x_wwdg.d1.65 kB2017-12-17|23:19
stm32f10x_wwdg.o371.44 kB2017-12-17|23:19
sys.crf342.48 kB2017-12-17|23:19
sys.d1.30 kB2017-12-17|23:19
sys.o375.83 kB2017-12-17|23:19
system_stm32f10x.crf341.32 kB2017-12-17|23:19
system_stm32f10x.d1.62 kB2017-12-17|23:19
system_stm32f10x.o371.02 kB2017-12-17|23:19
template.axf555.93 kB2017-12-17|23:19
template.build_log.htm204.00 B2017-12-18|10:43
template.hex31.47 kB2017-12-17|23:19
template.htm81.13 kB2017-12-17|23:19
template.lnp1.09 kB2017-12-17|23:19
template.sct479.00 B2017-11-26|10:06
usart.crf346.12 kB2017-12-17|23:19
usart.d1.46 kB2017-12-17|23:19
usart.o376.92 kB2017-12-17|23:19
01.97 kB
remote.c5.26 kB2017-12-07|12:43
remote.h877.00 B2017-12-07|12:51
01.97 kB
01.97 kB
delay.c7.74 kB2017-12-06|20:53
delay.h1.94 kB2017-12-06|20:53
01.97 kB
sys.c5.10 kB2017-12-17|23:19
sys.h2.98 kB2017-12-17|23:19
01.97 kB
usart.c4.97 kB2015-03-23|12:28
usart.h1.25 kB2012-09-13|14:17
01.97 kB
main.c4.46 kB2017-12-17|23:19
Release_Notes.html29.41 kB2011-04-06|18:15
startup_stm32f10x_hd.lst49.81 kB2017-12-17|23:19
stm32f10x.h619.08 kB2011-03-10|10:51
stm32f10x_conf.h3.18 kB2017-10-14|09:49
stm32f10x_it.c4.30 kB2011-04-04|19:03
stm32f10x_it.h2.04 kB2011-04-04|19:03
system_stm32f10x.c35.70 kB2011-04-04|19:03
system_stm32f10x.h2.04 kB2011-03-10|10:51
template.build_log.htm7.28 kB2017-10-14|09:38
template.map89.78 kB2017-12-17|23:19
template.uvgui.ZHENG70.76 kB2017-12-18|10:43
template.uvgui_ZHENG.bak70.58 kB2017-12-14|10:32
template.uvopt19.72 kB2017-12-07|15:36
template.uvproj21.42 kB2017-12-07|15:36
template_Target55.85 kB2017-12-17|23:19
template_uvopt.bak18.77 kB2017-11-26|10:06
template_uvproj.bak20.94 kB2017-11-26|10:06
云测速

stm32f10x_rcc.c (6.40 MB)

需要 1 积分
您持有 积分

CodeForge积分(原CF币)全新升级,功能更强大,使用更便捷,不仅可以用来下载海量源代码马上还可兑换精美小礼品了 了解更多

您的积分不足

支付宝优惠套餐快速获取 30 积分

订单支付完成后,积分将自动加入到您的账号。以下是优惠期的人民币价格,优惠期过后将恢复美元价格。

更多付款方式:网银PayPal

上传代码,免费获取

您本次下载所消耗的积分将转交上传作者。

同一源码,30天内重复下载,只扣除一次积分。

登录 CodeForge

还没有CodeForge账号? 立即注册
关注微博
联系客服

Switch to the English version?

Yes
CodeForge 英文版
No
CodeForge 中文版

完善个人资料,获价值¥30元积分奖励!

^_^"呃 ...

Sorry!这位大神很神秘,未开通博客呢,请浏览一下其他的吧
好的