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stm32f10x_usart.c ( 文件浏览 )

  • aaa923124003 发布于2018-04-23
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			/**
  ******************************************************************************
  * @file    stm32f10x_usart.c
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    11-March-2011
  * @brief   This file provides all the USART firmware functions.
  ******************************************************************************
  * @attention
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_usart.h"
#include "stm32f10x_rcc.h"

/** @addtogroup STM32F10x_StdPeriph_Driver
  * @{

  */

/** @defgroup USART 
  * @brief USART driver modules
  * @{

  */

/** @defgroup USART_Private_TypesDefinitions
  * @{

  */

/**
  * @
}
  */

/** @defgroup USART_Private_Defines
  * @{

  */

#define CR1_UE_Set                ((uint16_t)0x2000)  /*!< USART Enable Mask */
#define CR1_UE_Reset              ((uint16_t)0xDFFF)  /*!< USART Disable Mask */

#define CR1_WAKE_Mask             ((uint16_t)0xF7FF)  /*!< USART WakeUp Method Mask */

#define CR1_RWU_Set               ((uint16_t)0x0002)  /*!< USART mute mode Enable Mask */
#define CR1_RWU_Reset             ((uint16_t)0xFFFD)  /*!< USART mute mode Enable Mask */
#define CR1_SBK_Set               ((uint16_t)0x0001)  /*!< USART Break Character send Mask */
#define CR1_CLEAR_Mask            ((uint16_t)0xE9F3)  /*!< USART CR1 Mask */
#define CR2_Address_Mask          ((uint16_t)0xFFF0)  /*!< USART address Mask */

#define CR2_LINEN_Set              ((uint16_t)0x4000)  /*!< USART LIN Enable Mask */
#define CR2_LINEN_Reset            ((uint16_t)0xBFFF)  /*!< USART LIN Disable Mask */

#define CR2_LBDL_Mask             ((uint16_t)0xFFDF)  /*!< USART LIN Break detection Mask */
#define CR2_STOP_CLEAR_Mask       ((uint16_t)0xCFFF)  /*!< USART CR2 STOP Bits Mask */
#define CR2_CLOCK_CLEAR_Mask      ((uint16_t)0xF0FF)  /*!< USART CR2 Clock Mask */

#define CR3_SCEN_Set              ((uint16_t)0x0020)  /*!< USART SC Enable Mask */
#define CR3_SCEN_Reset            ((uint16_t)0xFFDF)  /*!< USART SC Disable Mask */

#define CR3_NACK_Set              ((uint16_t)0x0010)  /*!< USART SC NACK Enable Mask */
#define CR3_NACK_Reset            ((uint16_t)0xFFEF)  /*!< USART SC NACK Disable Mask */

#define CR3_HDSEL_Set             ((uint16_t)0x0008)  /*!< USART Half-Duplex Enable Mask */
#define CR3_HDSEL_Reset           ((uint16_t)0xFFF7)  /*!< USART Half-Duplex Disable Mask */

#define CR3_IRLP_Mask             ((uint16_t)0xFFFB)  /*!< USART IrDA LowPower mode Mask */
#define CR3_CLEAR_Mask            ((uint16_t)0xFCFF)  /*!< USART CR3 Mask */

#define CR3_IREN_Set              ((uint16_t)0x0002)  /*!< USART IrDA Enable Mask */
#define CR3_IREN_Reset            ((uint16_t)0xFFFD)  /*!< USART IrDA Disable Mask */
#define GTPR_LSB_Mask             ((uint16_t)0x00FF)  /*!< Guard Time Register LSB Mask */
#define GTPR_MSB_Mask             ((uint16_t)0xFF00)  /*!< Guard Time Register MSB Mask */
#define IT_Mask                   ((uint16_t)0x001F)  /*!< USART Interrupt Mask */

/* USART OverSampling-8 Mask */
#define CR1_OVER8_Set             ((u16)0x8000)  /* USART OVER8 mode Enable Mask */
#define CR1_OVER8_Reset           ((u16)0x7FFF)  /* USART OVER8 mode Disable Mask */

/* USART One Bit Sampling Mask */
#define CR3_ONEBITE_Set           ((u16)0x0800)  /* USART ONEBITE mode Enable Mask */
#define CR3_ONEBITE_Reset         ((u16)0xF7FF)  /* USART ONEBITE mode Disable Mask */

/**
  * @
}
  */

/** @defgroup USART_Private_Macros
  * @{

  */

/**
  * @
}
  */

/** @defgroup USART_Private_Variables
  * @{

  */

/**
  * @
}
  */

/** @defgroup USART_Private_FunctionPrototypes
  * @{

  */

/**
  * @
}
  */

/** @defgroup USART_Private_Functions
  * @{

  */

/**
  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
  * @param  USARTx: Select the USART or the UART peripheral. 
  *   This parameter can be one of the following values: 
  *      USART1, USART2, USART3, UART4 or UART5.
  * @retval None
  */
void USART_DeInit(USART_TypeDef* USARTx)
{

  /* Check the parameters */
  assert_param(IS_USART_ALL_PERIPH(USARTx));

  if (USARTx == USART1)
  {

    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
  
}
  else if (USARTx == USART2)
  {

    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
  
}
  else if (USARTx == USART3)
  {

    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
  
}    
  else if (USARTx == UART4)
  {

    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
  
}    
  else
  {

    if (USARTx == UART5)
    {
 
      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
    
}
  
}

}

/**
  * @brief  Initializes the USARTx peripheral according to the specified
  *         parameters in the USART_InitStruct .
  * @param  USARTx: Select the USART or the UART peripheral. 
  *   This parameter can be one of the following values:
  *   USART1, USART2, USART3, UART4 or UART5.
  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
  *         that contains the configuration information for the specified USART 
  *         peripheral.
  * @retval None
  */
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
{

  uint32_t tmpreg = 0x00, apbclock = 0x00;
  uint32_t integerdivider = 0x00;
  uint32_t fractionaldivider = 0x00;
  uint32_t usartxbase = 0;
  RCC_ClocksTypeDef RCC_ClocksStatus;
  /* Check the parameters */
  assert_param(IS_USART_ALL_PERIPH(USARTx));
  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
  /* The hardware flow control is available only for USART1, USART2 and USART3 */
  if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
  {

    assert_param(IS_USART_123_PERIPH(USARTx));
  
}

  usartxbase = (uint32_t)USARTx;

/*---------------------------- USART CR2 Configuration -----------------------*/
  tmpreg = USARTx->CR2;
  /* Clear STOP[13:12] bits */
  tmpreg &= CR2_STOP_CLEAR_Mask;
  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
  /* Set STOP[13:12] bits according to USART_StopBits value */
  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
  
  /* Write to USART CR2 */
  USARTx->CR2 = (uint16_t)tmpreg;

/*---------------------------- USART CR1 Configuration -----------------------*/
  tmpreg = USARTx->CR1;
  /* Clear M, PCE, PS, TE and RE bits */
  tmpreg &= CR1_CLEAR_Mask;
  /* Configure the USART Word Length, Parity and mode ----------------------- */
  /* Set the M bits according to USART_WordLength value */
  /* Set PCE and PS bits according to USART_Parity value */
  /* Set TE and RE bits according to USART_Mode value */
  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
            USART_InitStruct->USART_Mode;
  /* Write to USART CR1 */
  USARTx->CR1 = (uint16_t)tmpreg;

/*---------------------------- USART CR3 Configuration -----------------------*/  
  tmpreg = USARTx->CR3;
  /* Clear CTSE and RTSE bits */
  tmpreg &= CR3_CLEAR_Mask;
  /* Configure the USART HFC -------------------------------------------------*/
  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
  /* Write to USART CR3 */
  USARTx->CR3 = (uint16_t)tmpreg;

/*---------------------------- USART BRR Configuration -----------------------*/
  /* Configure the USART Baud Rate -------------------------------------------*/
  RCC_GetClocksFreq(&RCC_ClocksStatus);
  if (usartxbase == USART1_BASE)
  {

    apbclock = RCC_ClocksStatus.PCLK2_Frequency;
  
}
  else
  {

    apbclock = RCC_ClocksStatus.PCLK1_Frequency;
  
}
  
  /* Determine the integer part */
  if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
  {

    /* Integer part computing in case Oversampling mode is 8 Samples */
    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));    
  
}
  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
  {

    /* Integer part computing in case Oversampling mode is 16 Samples */
    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));    
  
}
  tmpreg = (integerdivider / 100) << 4;

  /* Determine the fractional part */
  fractionaldivider = integerdivider - (100 * (tmpreg >> 4));

  /* Implement the fractional part in the register */
  if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
  {

    tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
  
}
  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
  {

    tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
  
}
  
  /* Write to USART BRR */
  USARTx->BRR = (uint16_t)tmpreg;

}

/**
  * @brief  Fills each USART_InitStruct member with its default value.
 
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01.97 kB
01.97 kB
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stm32f10x_bkp.h7.38 kB2011-03-10|10:47
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stm32f10x_fsmc.h26.38 kB2011-03-10|10:47
stm32f10x_gpio.h19.70 kB2017-10-13|22:36
stm32f10x_i2c.h29.33 kB2011-03-10|10:47
stm32f10x_iwdg.h3.74 kB2011-03-10|10:47
stm32f10x_pwr.h4.28 kB2011-03-10|10:47
stm32f10x_rcc.h29.74 kB2011-03-10|10:47
stm32f10x_rtc.h3.77 kB2011-03-10|10:47
stm32f10x_sdio.h21.35 kB2011-03-10|10:47
stm32f10x_spi.h17.31 kB2011-03-10|10:47
stm32f10x_tim.h51.20 kB2011-03-10|10:47
stm32f10x_usart.h16.16 kB2011-03-10|10:47
stm32f10x_wwdg.h2.90 kB2011-03-10|10:47
01.97 kB
misc.c6.88 kB2011-03-10|10:47
stm32f10x_adc.c46.09 kB2011-03-10|10:47
stm32f10x_bkp.c8.26 kB2011-03-10|10:47
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stm32f10x_dma.c28.91 kB2011-03-10|10:47
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stm32f10x_sdio.c28.25 kB2011-03-10|10:47
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stm32f10x_tim.c106.60 kB2011-03-10|10:47
stm32f10x_usart.c37.41 kB2011-03-10|10:47
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stm32f10x_i2c.o382.00 kB2017-12-17|23:19
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stm32f10x_pwr.d1.62 kB2017-12-17|23:19
stm32f10x_pwr.o372.05 kB2017-12-17|23:19
stm32f10x_rcc.crf347.10 kB2017-12-17|23:19
stm32f10x_rcc.d1.62 kB2017-12-17|23:19
stm32f10x_rcc.o381.23 kB2017-12-17|23:19
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stm32f10x_rtc.o372.94 kB2017-12-17|23:19
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stm32f10x_sdio.d1.65 kB2017-12-17|23:19
stm32f10x_sdio.o378.45 kB2017-12-17|23:19
stm32f10x_spi.crf344.07 kB2017-12-17|23:19
stm32f10x_spi.d1.62 kB2017-12-17|23:19
stm32f10x_spi.o378.19 kB2017-12-17|23:19
stm32f10x_tim.crf361.76 kB2017-12-17|23:19
stm32f10x_tim.d1.62 kB2017-12-17|23:19
stm32f10x_tim.o404.37 kB2017-12-17|23:19
stm32f10x_usart.crf345.67 kB2017-12-17|23:19
stm32f10x_usart.d1.69 kB2017-12-17|23:19
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stm32f10x_wwdg.d1.65 kB2017-12-17|23:19
stm32f10x_wwdg.o371.44 kB2017-12-17|23:19
sys.crf342.48 kB2017-12-17|23:19
sys.d1.30 kB2017-12-17|23:19
sys.o375.83 kB2017-12-17|23:19
system_stm32f10x.crf341.32 kB2017-12-17|23:19
system_stm32f10x.d1.62 kB2017-12-17|23:19
system_stm32f10x.o371.02 kB2017-12-17|23:19
template.axf555.93 kB2017-12-17|23:19
template.build_log.htm204.00 B2017-12-18|10:43
template.hex31.47 kB2017-12-17|23:19
template.htm81.13 kB2017-12-17|23:19
template.lnp1.09 kB2017-12-17|23:19
template.sct479.00 B2017-11-26|10:06
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usart.d1.46 kB2017-12-17|23:19
usart.o376.92 kB2017-12-17|23:19
01.97 kB
remote.c5.26 kB2017-12-07|12:43
remote.h877.00 B2017-12-07|12:51
01.97 kB
01.97 kB
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delay.h1.94 kB2017-12-06|20:53
01.97 kB
sys.c5.10 kB2017-12-17|23:19
sys.h2.98 kB2017-12-17|23:19
01.97 kB
usart.c4.97 kB2015-03-23|12:28
usart.h1.25 kB2012-09-13|14:17
01.97 kB
main.c4.46 kB2017-12-17|23:19
Release_Notes.html29.41 kB2011-04-06|18:15
startup_stm32f10x_hd.lst49.81 kB2017-12-17|23:19
stm32f10x.h619.08 kB2011-03-10|10:51
stm32f10x_conf.h3.18 kB2017-10-14|09:49
stm32f10x_it.c4.30 kB2011-04-04|19:03
stm32f10x_it.h2.04 kB2011-04-04|19:03
system_stm32f10x.c35.70 kB2011-04-04|19:03
system_stm32f10x.h2.04 kB2011-03-10|10:51
template.build_log.htm7.28 kB2017-10-14|09:38
template.map89.78 kB2017-12-17|23:19
template.uvgui.ZHENG70.76 kB2017-12-18|10:43
template.uvgui_ZHENG.bak70.58 kB2017-12-14|10:32
template.uvopt19.72 kB2017-12-07|15:36
template.uvproj21.42 kB2017-12-07|15:36
template_Target55.85 kB2017-12-17|23:19
template_uvopt.bak18.77 kB2017-11-26|10:06
template_uvproj.bak20.94 kB2017-11-26|10:06
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