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Vhdl 语言中 16 位时间域卷积

卷积是在数字信号处理的常见操作。在此项目中,我创建了自定义电路利用大量的并行机制以提高性能与微处理器相比在 Nallatech 主板上实施。卷积将作为输入信号和 kernell 输出是另一个信号,输出信号的每个元素在哪里乘以内...
  VHDL      VHDL     

Verilog 编写的IP核,512K的16位SRAM

Verilog 编写的IP核,512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM...
  VHDL        Others     

基于SRAM的可重配置电路

基于SRAM的可重配置电路-SRAM-based reconfigurable circuit...
  文档处理        Others     

主要讲解SRAM_512k61LV25616的时序及其原理

主要讲解SRAM_512k61LV25616的时序及其原理-Mainly on the timing and the Principle SRAM_512k61LV25616...
  嵌入式系统        Others     

FPGA控制的SRAM接口不分的设计

FPGA控制的SRAM接口不分的设计-FPGA-controlled SRAM interface design, regardless of...
  VHDL      VHDL     

SRAM 读写小程序,用verilog编写的,请各位高手指教

SRAM 读写小程序,用verilog编写的,请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master...
  VHDL        Others     

SRAM Controller For Altera SOPC Builder and NIOS on DE2 kit board...

SRAM Controller For Altera SOPC Builder and NIOS on DE2 kit board...
  嵌入式系统        Others     

This leon3 design is tailored to the Altera NiosII Startix2 Development board...

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR ena...
  VHDL        Others     

FPGA读SRAM中的数再传给CY7C68013

FPGA读SRAM中的数再传给CY7C68013-Reading SRAM in the FPGA, then pass on a few CY7C68013...
  VHDL        Others     

FPGA将从CY7C68013读到的数写入SRAM

FPGA将从CY7C68013读到的数写入SRAM-FPGA will read a few CY7C68013 write SRAM...
  VHDL        Others     

FPGA向SRAM中写入数据,VHDL编程

FPGA向SRAM中写入数据,VHDL编程-FPGA to the SRAM write data, VHDL programming...
  VHDL        Others     

TI28xDSP,SRAM内存数据访问源码文件。

TI28xDSP,SRAM内存数据访问源码文件。-TI28xDSP, SRAM memory data access source files....
  DSP设计        Others     

用verilog实现的epp与SRAM通信的程序

用verilog实现的epp与SRAM通信的程序-epp communicate with SRAM in verilog...
  通信      VHDL     

一个比较有参考价值的SRAM IP核,对SOPC感兴趣的人士有一定的...

一个比较有参考价值的SRAM IP核,对SOPC感兴趣的人士有一定的指导意义!该程序是采用avalon总线,可以直接内嵌进SOPC Builder。-A comparison reference value has SRAM IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, ca...
  VHDL        Others     

这本书是不多见的hspice指导书,里面对hspice的语法、电路仿真...

这本书是不多见的hspice指导书,里面对hspice的语法、电路仿真的诸多细节均详细给出,很适合IC设计人员参阅!-This book is a guideline for a IC designer!...
  电子书        PDF     

FPGA的SRAM存储器的控制程序,包括时序测试

FPGA的SRAM存储器的控制程序,包括时序测试-FPGA...
  VHDL      VHDL     

hspice tool box in matlab...

hspice tool box in matlab...
  Windows开发        Others     

orcad 库_IC设计专用

orcad 库_IC设计专用...... symbol用于管级原理图绘制...... 生产网表供hspice/pspice仿真...... 写论文专用.........
  Windows开发      VHDL     

描述 SRAMoc ( K , M ) 表示用数字0、1、2…、K

描述 SRAMoc ( K , M ) 表示用数字0、1、2…、K-1组成的自然数中能被M整除的最小数。给定 K、M,求SRAMoc ( K,M )。例如 K=2,M=7的时候,SRAMoc( 2 , 7 ) = 1001。 输入 第一行为两个整数K、M满足2<=K<=10、1<=M<=1000。 输...
  VHDL        C++     

本程序用于测试实时时钟模块SD2000的SRAM存储器D/E系列, 程序...

本程序用于测试实时时钟模块SD2000的SRAM存储器D/E系列, 程序功能如下: 1. 关闭/INT1及/INT2的中断输出 2. 初始化时间(写时间数据) 3. 在BREAKPOINT1设断点时,依次读时间-写SRAM数据-读SRAM数据循环 4. 全速执行时,LED四位分别显示小时和...
  其他项目        Others     

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