//4entrydeepfastfifo
modulefifo4(clk,rst,clr, din,we,dout,re,full,empty);
parameterdw=8;
inputclk,rst;
inputclr;
input [dw:1]din;
inputwe;
output [dw:1]dout;
inputre;
outputfull,empty;
////////////////////////////////////////////////////////////////////
//
//LocalWires
//
reg [dw:1]mem[0:3];
reg [1:0] wp;
reg [1:0] rp;
wire [1:0] wp_p1;
wire [1:0] wp_p2;
wire [1:0] rp_p1;
wirefull,empty;
reggb;
///////////////////////////////////